The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device which has vertical pillar transistors and can reduce the resistance of buried bit lines and a method for manufacturing the same.
As the integration level of semiconductor devices increases, the area that is occupied by each unit cell when viewed from the top has decreased. In order to accommodate the reduction in the unit cell area, various methods for forming transistors, bit lines, word lines, and capacitors in a limited area have been researched.
In one method, a semiconductor device having vertical pillar transistors, in which source areas and drain areas are located up and down in an active region to form vertical channels, has been proposed.
The vertical pillar transistor is formed in a manner such that a gate is formed in the sidewall of a silicon pillar constituting an active region, a source area is formed in the upper portion of the silicon pillar over the gate, and a drain area is formed in a silicon substrate under the silicon pillar.
In the semiconductor device having vertical pillar transistors, a cell scheme is decreased from 8F2 to 4F2; and thus the net die can be remarkably increased, and gate driving force can be increased due to the formation of a surrounding gate. In particular, in the semiconductor device having vertical pillar transistors, the channel length does not decrease even though the area of the transistor is decreased, and therefore the characteristics and the reliability of the semiconductor device can be elevated.
Meanwhile, while not concretely shown in a drawing, in the conventional semiconductor device having vertical pillar transistors, the bit lines are formed in a buried style by ion-implanting N-type impurities in the silicon substrate. Because of this fact, the resistance of the buried bit lines increases several thousand times when compared to the resistance of bit lines in the semiconductor device having planar channel transistors. Due to this fact, the semiconductor device having vertical pillar transistors suffers from defects in that current decreases, RC delay increases, and current driving capability is deteriorated.
Therefore, in the semiconductor device having vertical pillar transistors, the resistance of the bit lines must be necessarily reduced.